module yiwei_register(clk, din, dout,rst);  
 
 input clk,rst;  
 input [3:0] din;  
 output reg[3:0] dout;    
 
 always @(posedge clk) begin
	if (rst)
		dout = 0;
	else
		dout = {din[0], din[3:1]};
end  
 
endmodule
